RE: Meeting minutes 050825

Hi John,

Should I assume that the latest Revision you have sent (I believe this
was Revision 1.5) is compatible with your statement here (about no
requiring any language extensions) or do you plan to publish a different
revision that you see as compatible with this statement.

Please clarify.

Thanks, 

>And with some of the recent proposals we've been discussing,
>all function declarations can be made via attributes which
>are part of both Verilog and VHDL. So if people are uncomfortable
>with pragmas, this is another approach that is fully consistent
>with existing, supported language features and requires no
>langauage extensions as you suggest below.
>
>-- johns