Shabtay, My apologies, I've been literally without e-mail access for the last week straight and am just getting to this now. As of rev 1.5, I think pragma syntax is still shown for import/export decl syntax (attribute syntax for data type qualifiers), but I think we can be open to making this attribute based as well. -- johnS Shabtay Matalon wrote: > Hi John, > > Should I assume that the latest Revision you have sent (I believe this > was Revision 1.5) is compatible with your statement here (about no > requiring any language extensions) or do you plan to publish a different > revision that you see as compatible with this statement. > > Please clarify. > > Thanks, > > >And with some of the recent proposals we've been discussing, > >all function declarations can be made via attributes which > >are part of both Verilog and VHDL. So if people are uncomfortable > >with pragmas, this is another approach that is fully consistent > >with existing, supported language features and requires no > >langauage extensions as you suggest below. > > > >-- johns > > -- This email may contain material that is confidential, privileged and/or attorney work product for the sole use of the intended recipient. Any review, reliance or distribution by others or forwarding without express permission /\ is strictly prohibited. If you are /\ | \ not the intended recipient please | \ / | contact the sender and delete / \ \ all copies. /\_/ K2 \_ \_ ______________________________/\/ \ \ John Stickley \ \ \ Mgr., Acceleration Methodologies \ \________________ Mentor Graphics - MED \_ 17 E. Cedar Place \ john_stickley@mentor.com Ramsey, NJ 07446 \ Phone: (201) 818-2585 ________________________________________________________________Received on Thu Sep 15 08:10:41 2005
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