RE: SCE-MI 2.0 HDL Support (Re: Meeting minutes 050825)

Hi Shabtay,

Per> The choice of HDL should be transparent to the software side,
Per> i.e., the user should be able to use Verilog 2001, SystemVerilog,
Per> and VHDL interchangeably without having to rewrite the software
Per> side

Shabtay> Very important goal that should be attempted, but one that
Shabtay> cannot override the other principles.

Shabtay> I didn't state that defining a function based interface in old
Shabtay> Verilog/Verilog 2001 and/or VHDL is impossible. John's latest
Shabtay> proposal doesn't meet the principles I outlined. If there are
Shabtay> other proposals that do, we should evaluate them.

As far as I could tell, the only reason you are rejecting John's
proposal is that according to Cadence's analysis there is no way
to implement it in a standard simulator without some degree of
`code regeneration'.  Is this correct?

I'd like to understand why Cadence sees code regeneration as such
a big problem?  And why do you not have the exact same issue in
a macro based approach in SCE-MI 1.1 as well as 2.0?  Certainly,
this would be the case in strict VHDL, wouldn't it?  In strict VHDL
you can't add the SCE-MI 1.1 infrastructure without changing the
code to some degree.  In Verilog you probably can get by using
cross-module references to some degree, but I suspect that even
in Verilog code must be added to actually implement the SCE-MI
infrastructure.  So I am wondering why Cadence sees code regeneration
as a big problem?  Note, I am not saying that it is actually
required.  I'd like to hear John's response to your questions
to him on that topic as well.  But assuming the worst case, why
is Cadence opposed to implementing the infrastructure linker as
a sort of preprocessor that dumps out modified code that is then
passed to the target?

Thanks,
Per

-- 
Per Bojsen                                Email: <bojsen@zaiqtech.com>
Zaiq Technologies, Inc.                   WWW:   http://www.zaiqtech.com
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