Accellera SV-AC Technical Committee
	Extensions and Errata
Rev 1.9	#####	Enhancement List for System Verilog Assertions
11/19/2003
Assertion Enhancements for SV-AC in SV v3.1a
Item Number	Item Name	Enhancement Description	Proposals	Author	Scheduled Review
1	Addl_prop_directive	Adding assume directive for concurrent assertions	Proposal	Surrendra	12/8/03
2	assume_sync	Allowing sequential properties in constraint blocks	Proposal	Surrendra	12/8/03
3		Accessing local variables via ended and matched functions	Proposal	John	12/1/03
4	local_var_ext	Attaching local variable assignments to a sequence expression	Proposal	John	12/1/03
5	clock_var_assign	Allowing auxiliary modeling using temporal functions	Proposal	Surrendra	12/8/03
6	clock_var_access	Allow accessing sampled values using a new $sampled function	Proposal	Surrendra	12/8/03
7	inf_pass_arg	Allow passing of unbounded range as argument to properties and sequences	Proposal	Surrendra	12/8/03
8	assert_in_func	Allow assertions to be used within functions in procedural scope.	Proposal	Adam	12/1/03
9	gated_clk_support	Extend $past function to support gated clocks	Proposal	Surrendra	12/8/03
10		Extend modport to allow passing of assertion statements	Proposal	Adam	12/1/03
11		Extend properties to allow dynamic and recursive calls to a property.	Proposal	John	12/1/03
12		Relax rules for clock specification for multi-clock sequences and properties	Proposal	John	12/1/03
13		Allow a consequent of an implication to be any property expression, thereby providing for  nesting of implications	Proposal	John	12/1/03
14		Allow boolean conjunction of properties as a property expression	Proposal	John	12/1/03
15		Allow boolean disjunction of properties as a property expression	Proposal	John	12/1/03
16		Allow if-else combination of properties as a property expression	Proposal	John	12/1/03
17		Allow a property instance an a property expression	Proposal	John	12/1/03
18		Allow boolean negation of a property as a property expression	Proposal	John	12/1/03
19		Error or message reporting from within a property	?	Adam,John,Surrendra
20		Support parameters for assertions, extend to allow sequence as parameter	Proposal	Joseph	12/8/03
21		assume directive that must hold for all times (assumed immediate)	Proposal	Joseph	12/8/03
Assertion Related Enhancements Target by other Sub-Committee
22	event_temporal	general clocked event object triggered on completion of assertion, handled similar to other verilog events	SV-EC
23	expect_temporal	extend expect (blocking wait) to support wait on in-lined sequence event or named clocked event completion	SV-EC
24	embed_struct	feature to embed assertions within a user defined type (typedef), assertion will be checked in every instantiation of struct	SV-BC
Enhancements for consideration beyond v3.1a			Sub-Committee	N/A	N/A
25	template	template feature (should be passed to BC)	SV-BC	N/A
26	neg_delay	extend time windows to allow negative delays	SV-AC	N/A
27	embed_class	assertions on variables, classes, dynamic objects	SV-AC	N/A
28	temp_operators	allow additional temporal operators for increased expressiveness (omega regular language)	SV-EC	N/A
29	formal_features	more formal features in language	SV-AC	N/A
Errata List for SV v3.1a
Item #
081003.AC1		throughout associativity, change to right
081003.AC2		unary ## should have the higher precedence than binary ##
081003.AC3		allow clocked sequences(including multi-clock) to be parenthesized
081003.AC4		language force parenthesis around the expression with local variable assignments
081003.AC6		formal semantics needs to define meaning of multiple local variables attached to a single boolan
081003.AC7		need to define neutral trace semantics, in alignment with PSL
AC8		Implication operator erratum	Proposal	Adam