System Verilog
Extension Proposals
ID	Priority	Extension:	Owner:	Proposals:	Status:
EXT-2	1	Constraints/Randomization	Mehdi M.	Proposal	Approved
EXT-18	1	Handles	SV-CC	Requirements	Approved
				Proposal
EXT-19	1	Scheduling Semantics	Phil Moorby	Discussion	Approved
EXT-20	1	Export/Extern	SV-CC	Requirements	Approved from SV-CC. CH-120 contains proposal from SV-CC.
				Proposal
EXT-3	2	Alias	Cliff C./Kevin C.	Alias Proposal	Approved
				Alias Proposal Update
				Alias Proposal Update 2
				Alias Proposal Update 3
				Alias Proposal Final
EXT-1	1	References	Kevin C.	References	This is replaced by EXT-18 from SV-CC.
				References Refined
				Full Proposal
EXT-4	3	Interface Scheduling	Stuart S.	Requirements	3.2
EXT-5	3	Interface Usage	Stuart S.	Requirements	3.2
EXT-6	3	Modports	Stuart S.	Requirements	3.2
EXT-7	3	Process Control	Kevin C.	Requirements	3.2
				Requirements Clarification
				Proposal
				Proposal Refined
				Proposal Refined Again
EXT-8	4	Data Channels	Kevin C.	Channels	3.2
				Channel Requirements
EXT-9	5	FSM (original ESS donation)	Cliff C.	No new	3.2
EXT-10	6	Extern Modules		None	3.2
EXT-11	7	Inferred Reg Types	Cliff C./Kevin C.	None	3.2
EXT-12	8	Multi-clock/Hier. FSM		None	3.2
EXT-13	9	Data Path	Proposed Cadence donation	None	3.2
EXT-14	10	Pointers	Kevin C.	None	3.2
EXT-15	11	Inherited Declarations		None	3.2
EXT-16	12	Force/release with strengths		None	3.2
EXT-17	13	OO	Kevin C./Vassilios G.	No seperate donation (included in testbench)	Closed
EXT-21	-	Compatibility directive	Stu Sutherland	Stu's Proposal	3.2
				Notes:
					These extensions have no proposals or were prioritized below the cut line for 3.1. The extension may be addressed through an existing donation.
					The reference extension has been prioritized as first due to the requirement from SV-CC for opaque pointers and SV-BC for pass-by-reference semantics for structures.
					There are more than one number one priority since we have to respond to all requirements placed on us from other committees.