Subject: Re: Untimed behavioral Verilog-D & Connect modules
From: Jonathan Sanders (jons@cadence.com)
Date: Sun Feb 11 2001 - 00:58:05 PST
Kevin,
This is one that I think we need to get the digital committee to address as
this
is core language and has little to do with our analog extensions to it. I
suggest
running this request by Stu Sutherland and others on that committee.
Jon
At 09:51 AM 2/9/01, Kevin Cameron x3251 wrote:
>
> > Kevin,
> >
> > As far as I can tell all OOMRs must be given a full hierarchical path.
> > Thus the reason that we create a second top level block for these
> > references as we can then from any block give the path as shown
> > in my previous email on this.
> >
> > Jon
>
>I would suggest a syntax for "parent" if I could think of a good one
>('..' looks too much like a typo) - maybe '*' for a wildcard match?
>
>Suggestions welcome.
>
>Kev.
>
> > At 05:26 PM 2/8/01, Kevin Cameron x3251 wrote:
> >
> > >Marginally related to OOMR and "driver update" stuff.
> > >
> > >It crossed my mind that if I do have an "unreliable" driver
> > >(http://www.eda.org/verilog-ams/htmlpages/tc-docs/issues/0004/)
> > >I may want to use a clock associated with the data and setup time
> > >specs instead. This is also related to where connect modules are
> > >placed (http://www.eda.org/verilog-ams/htmlpages/tc-docs/issues/0003/)
> > >as it probably necessary to use an OOMR to reach the relevent clock.
> > >
> > >Is there an OOMR syntax equivalent of the Unix '..' ?
> > >
> > >Kev.
***********************************************************
Jonathan L. Sanders
Product Engineering Director
Mixed Signal and Physical Verification Solutions
Cadence Design Systems, Inc.
555 River Oaks Pkwy
San Jose, CA. 95134
INTERNET:jons@cadence.com Tel: (408) 428-5654 Fax : (408) 944-7265
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