Subject: Re: Untimed behavioral Verilog-D & Connect modules
From: Pragmatic C Software (sjmeyer@pragmatic-c.com)
Date: Mon Feb 12 2001 - 09:25:24 PST
Quoting Kevin Cameron x3251 (Kevin.Cameron@nsc.com):
>
> > Kevin,
> >
> > As far as I can tell all OOMRs must be given a full hierarchical path.
> > Thus the reason that we create a second top level block for these
> > references as we can then from any block give the path as shown
> > in my previous email on this.
> >
> > Jon
>
> I would suggest a syntax for "parent" if I could think of a good one
> ('..' looks too much like a typo) - maybe '*' for a wildcard match?
>
There is already a mechanism in P1364 Verilog for "parent" references.
They are called upward relative references. The first component can
be either a module name or an instance name. The search rule is start
by assumidesign first component is upward instance searching upward until root
is seen. If not found, assume first component of name is module type name
and repeat process, but again this feature is mostly avoided since it
makes it harder for modules to be re-usable, i.e. the module needs to
know the design context in which it is instantiated.
/Steve
<removed old messages>
-- Steve Meyer sjmeyer@pragmatic-c.com
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