Subject: Re: Untimed behavioral Verilog-D & Connect modules
From: Kevin Cameron x3251 (Kevin.Cameron@nsc.com)
Date: Fri Feb 09 2001 - 09:51:32 PST
> Kevin,
>
> As far as I can tell all OOMRs must be given a full hierarchical path.
> Thus the reason that we create a second top level block for these
> references as we can then from any block give the path as shown
> in my previous email on this.
>
> Jon
I would suggest a syntax for "parent" if I could think of a good one
('..' looks too much like a typo) - maybe '*' for a wildcard match?
Suggestions welcome.
Kev.
> At 05:26 PM 2/8/01, Kevin Cameron x3251 wrote:
>
> >Marginally related to OOMR and "driver update" stuff.
> >
> >It crossed my mind that if I do have an "unreliable" driver
> >(http://www.eda.org/verilog-ams/htmlpages/tc-docs/issues/0004/)
> >I may want to use a clock associated with the data and setup time
> >specs instead. This is also related to where connect modules are
> >placed (http://www.eda.org/verilog-ams/htmlpages/tc-docs/issues/0003/)
> >as it probably necessary to use an OOMR to reach the relevent clock.
> >
> >Is there an OOMR syntax equivalent of the Unix '..' ?
> >
> >Kev.
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