Subject: A2D Error
From: Kevin Cameron x3251 (Kevin.Cameron@nsc.com)
Date: Thu Jan 02 2003 - 12:12:09 PST
The attached document should clarify the issue some.
New text for 9.3.2.3 para 2 to:
For the purpose of reporting results and scheduling delayed future
events, the digital kernel rounds A2D event times such that error
is limited to the smaller of half the precison base for the module whose
port is being connected or the precision base of the connect module. For
the examples below the timescale is 1ns/1ns, so the maximum scheduling
error when swapping a digital module for it's analog counterpart
will be 0.5ns.
A2D statements that do not include a scheduling delay are processed
immediately in a new digital simulation cycle such that dependent
zero-delay
non-blocking assigns are executed before control returns to the
analog domain.
Regards,
Kev.
-- National Semiconductor, Tel: (408) 721 3251 2900 Semiconductor Drive, Mail Stop D3-500, Santa Clara, CA 95052-8090
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