Subject: Re: A2D Error
From: Kevin Cameron x3251 (Kevin.Cameron@nsc.com)
Date: Mon Jan 06 2003 - 17:52:33 PST
New text for 9.3.2.3 para 2 to:
For the purpose of reporting results and scheduling delayed future
events, the digital kernel converts analog event times to digital times
such that error is limited to half the precison base for the module where
the conversion occurs. For the examples below the timescale is 1ns/1ns, so
the maximum scheduling error when swapping a digital module for it's analog
counterpart will be 0.5ns. A2D statements that do not include a scheduling
delay are processed immediately in a new digital simulation cycle such that
dependent zero-delay non-blocking assigns are executed before control returns
to the analog domain.
Regards,
Kev.
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