Subject: Re: Infinity in Verilog-AMS
From: Geoffrey.Coram (Geoffrey.Coram@analog.com)
Date: Tue Apr 29 2003 - 09:50:32 PDT
Kevin -
Infinity still exists as a keyword in OVI-2.0, because
you can say
parameter real BV = 30 from [0:inf);
You just can't say
parameter real BV = inf from [0:inf];
So I'm not asking to add a keyword.
-Geoffrey
Kevin Cameron x3251 wrote:
> Don't know, but I'm sure we can add it back in.
>
> Note: due to issues with adding keywords it's preferable
> to declare things like 'inf' in standard header files
> (like in C). SystemVerilog has a "$root" scope where
> you can declare things like numeric constants (rather
> than using `define).
>
> Kev.
-- Geoffrey J. Coram, Ph.D. Senior CAD Engineer Analog Devices, Inc. Geoffrey.Coram@analog.com 804 Woburn St., MS-422, Tel (781) 937-1924 Wilmington, MA 01887 Fax (781) 937-1014
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