Kevin -
I found more detail about generate in 1364-2005-d2.pdf
(http://www.boyd.com/1364/1364-2005-d2.pdf.gz)
and it doesn't work at all for paramsets. Generate
statements must lie within a module, but paramsets
(and their spice "equivalent", .model cards) are
set up independent of the module.
The way paramsets are proposed, one might even choose
to have a particular instance simulated by one of two
different modules.
-Geoffrey
I wrote:
> > I could not find a section about "generate" in the SV LRM,
and Kevin Cameron replied:
>
> It's in the Verilog 200X LRM (I don't have a copy handy).
> generate statements are evaluated at elaboration time dependent
> on parameters etc. and let you choose different sub-modules and
> behavior.
Received on Mon Apr 5 12:02:24 2004
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