Re: V-AMS DevModeling meeting April 6, new proposal doc

Geoffrey.Coram wrote:

>David -
>We don't need "ref" as a keyword, so I don't see any reason to
>inflict that pain now. The merge with SystemVerilog will likely
>cause a lot of pain, and it could destroy Verilog-A if that
>merge were done in pieces, so every N months, everyone has to go
>through the whole library of Verilog-A modules and figure out
>what needs to be changed.
>
>I also wouldn't be surprised if a number of Spice simulators
>only ever implemented Verilog-A 2.2 (or whatever these
>extensions become) -- not even the full AMS.
>
>-Geoffrey
>
The aim of this committee when it was originally set up was to bring
analog simulation
into the Verilog language. The Verilog-A subset was only supposed to be
an interim
landmark, not stand-alone language standard.

Due to procrastination and politics the Verilog standard has moved
entirely to the IEEE
without Verilog-A[MS], and Accellera is now concentrating on
SystemVerilog. So the
primary goal "one HDL for analog and digital" now means integration with
SystemVerilog.

Kev.

>"David W. Smith" wrote:
>
>
>>Just a quick comment. You are going to have to eventually accept all of the new keywords in SystemVerilog anyway so the argument that ref may collide (while true) is not particularly relevant. Changing the syntax will not be an option since SystemVerilog is now an approved standard.
>>
>>Regards
>>
>>David
>>
>>

-- 
Kevin Cameron, CPU Technology, CA 94588, Tel.: (925) 225 4862