AMS/SV integration and adoption of Verilog-A

Kevin Cameron wrote:
> IMO the lack of integration is probably stopping adoption as much as
> anything else.

If you mean, the lack of integration between Verilog-A/MS
and Verilog-2001/SystemVerilog is stopping adoption of
Verilog-A, I would have to disagree for the compact
modeling community.

I was at the Workshop on Compact Modeling (part of NanoTech2004),
and SystemVerilog never came up. What came up were things like
proprietary extensions (a MOS model wouldn't work in company A's
simulator because it had extensions for company B's) and
inconsistent or wrong implementations of the existing
Verilog-A standard, archaic though it is (a BJT model gave
incorrect AC analysis results because sqrt(x) in one company's
simulator has a derivative of 1/sqrt(x+epsilon), lest there
be a division by zero, but "epsilon" dominated x).

Several speakers noted the need for a cross-simulator standard
modeling language. The modeling community is having trouble
keeping up with shrinking technology: the Compact Model Council
is searching for a next-generation MOS model for 65nm and below,
but selection won't happen until next summer, and meanwhile
there are companies building 45nm transistors and trying to get
something to designers to see if you can make a working circuit
with those devices.

If you can write your model in Verilog-A and get it into whatever
(Spice-like) analog simulator quickly, your designers can feed
back to you about how to improve the transistor so they can
build an inverter, nand gate, etc. You probably don't care
whether this Verilog-A is then integrated into a SystemVerilog
solution for full chip design, because the full-chip design
is probably done with standard cells.

-Geoffrey
Received on Wed Apr 7 07:16:43 2004