Re: AMS/SV integration and adoption of Verilog-A

Geoffrey.Coram wrote:

>Kevin Cameron wrote:
>
>
>>IMO the lack of integration is probably stopping adoption as much as
>>anything else.
>>
>>
>
>If you mean, the lack of integration between Verilog-A/MS
>and Verilog-2001/SystemVerilog is stopping adoption of
>Verilog-A, I would have to disagree for the compact
>modeling community.
>
>
That's the problem in a nutshell, it's great that Veriilog-A is
replacing Spice for some communities, but Accellera's original aim (OVI
at the time) was that there should be one language for all communities.

>I was at the Workshop on Compact Modeling (part of NanoTech2004),
>and SystemVerilog never came up. What came up were things like
>proprietary extensions (a MOS model wouldn't work in company A's
>simulator because it had extensions for company B's) and
>inconsistent or wrong implementations of the existing
>Verilog-A standard, archaic though it is (a BJT model gave
>incorrect AC analysis results because sqrt(x) in one company's
>simulator has a derivative of 1/sqrt(x+epsilon), lest there
>be a division by zero, but "epsilon" dominated x).
>
>Several speakers noted the need for a cross-simulator standard
>modeling language. The modeling community is having trouble
>keeping up with shrinking technology: the Compact Model Council
>is searching for a next-generation MOS model for 65nm and below,
>but selection won't happen until next summer, and meanwhile
>there are companies building 45nm transistors and trying to get
>something to designers to see if you can make a working circuit
>with those devices.
>
>If you can write your model in Verilog-A and get it into whatever
>(Spice-like) analog simulator quickly, your designers can feed
>back to you about how to improve the transistor so they can
>build an inverter, nand gate, etc. You probably don't care
>whether this Verilog-A is then integrated into a SystemVerilog
>solution for full chip design, because the full-chip design
>is probably done with standard cells.
>
>-Geoffrey
>
When I did hardware design I worked on mixed signal circuits like
Switch-Mode Power Supplies, those kind of designs mix high power single
transistors, inductors, capacitors etc. and digital control logic.
That was board level stuff so I could bread-board it easily and didn't
have to simulate it. These days most of the bits are integrated into
single chips and can't be bread-boarded so simulation is the only way to
design and verify. It is crucial that [System]Verilog-AMS is a single
language that can describe high level logic down to single transistors
(and works equally well for all the designers) if mixed signal SoC is to
be commercially viable for more than a few (wealthy) design houses.

Kev.

-- 
Kevin Cameron, CPU Technology, CA 94588, Tel.: (925) 225 4862