RE: LRM Committee meeting

>-----Original Message-----
>From: owner-verilog-ams@eda.org [mailto:owner-verilog-ams@eda.org] On
>Behalf Of Chandrasekaran Srikanth-A12788
>Sent: Sunday, January 09, 2005 11:44 PM
>To: Verilog-AMS LRM Committee
>Subject: LRM Committee meeting
>
>
>Hi all,
>
>I would like to schedule the next LRM committee meeting on the 17th of
>January, 1:30pm Pacific time (instead of 10th January as per the original
>plan that we decided in our last call). Hope this is fine with everybody
>and apologize for the late notice for changing the date.
>
>Martin,
>Would it be possible to send the updated proposal for the $table_model that
>was being worked upon?

Yes I will give an update on this topic. I have been some input from additional input from customers that I would like to bring to the committee and I would also like to present what I have captured from the discussions so far.

Thanks,
--Martin

>
>Also there was a request from Micahel Mirmak of IBIS forum (I/O buffer
>Information Spec) to make a presentation to the VerilogAMS committee and
>would like to discuss this as part of the agenda.
>
>I would send a complete agenda during the week.
>
>Regards,
>Sri
>--
>Srikanth Chandrasekaran
>Freescale Semiconductors, Australia
>Ph: +61-8-8168 3592 Fax: 3501
Received on Tue Jan 11 21:38:09 2005