Re: Updated Syntax with Device Model updates (on behalf of Graham)

Graham -
A few notes on syntax 2.3 draft:

1) In the introduction, item 1. says that 1364-2001 Verilog items
are in blue with cyan keywords, but the keywords are magenta
(pink) not cyan (light blue).

2) All the italics have been lost, eg, real_identifier should
have "real" italicized.

3) I agree with both of these changes:
> - String parameters have been inserted as another type of
> normal and local parameter declaration.
> - Alias parameter declarations now support multiple assignments
> in order to be consistent with other declarations.

but the syntax of the latter should be
  alias_param_assignment ::= alias_identifier = parameter_identifier
not
  alias_param_assignment ::= parameter_identifier = parameter_identifier

(and on the RHS, alias and parameter should be italicized)

4)
> - Alias parameter declarations are not supported in the
> module_parameter_port_list syntax item.

That looks OK to me; I'm not familiar with the syntax that
uses this.

5)
> - Paramset declarations:
> - Does not support array parameter assignments.
> - change module_parameter_identifier to be
> parameter_identifier to be consist with rest of syntax.

(You have "delcaration" a few times in this section.)

I still see .array_param_assignment as a valid paramset_statement;
what did you mean by "does not support array parameter assignments"?

The sematics needs to be clarified for the .param_assignment;
I wasn't clear on this point in LRM 2.2: if you have a paramset
on a paramset, then the .param_assignment applies to the underlying
paramset, not the ultimate module under it all. Eg:

paramset nmos_18u_fast nmos_18u;
  (set vth for the high corner, pass l and w)

paramset nmos_18u bsim3v3;
  (fix values for bsim3v3 model, allow "instance" values l,w,vth)

module bsim3v3 (d,g,s,b);

The paramset "nmos_18u_fast" can only set values for the
parameters of the "nmos_18u" paramset, NOT values for the
bsim3v3 module.

6)
> - String parameter declarations use string syntax item
> for the default expression (not string_constant_expression).

I think this is OK, but I'm a little concerned that SystemVerilog
has string variables, and we want to be clear that string in
our LRM means a fixed string.

7)
> - System parameter identifiers use the same naming convention
> as system function/task identifiers

This is good, now that these identifiers have a syntax rather than
the syntax simply listing all of the defined ones.

8) Two comments on this item:
> - Simplified the ddx() operator's optional 2nd argument syntax,
> use semantic check to restrict it further if required.

The ddx() operator needs BOTH arguments, the second is not optional.
And the 2.2 LRM just has ddx as an analog_operator with an arg_list,
so you've actually complicated the syntax in Annex A. Is there a
push to have Annex A be more specific about the arguments?

-Geoffrey

-- 
Geoffrey J. Coram, Ph.D.    Senior CAD Engineer     
Analog Devices, Inc.        Geoffrey.Coram@analog.com 
804 Woburn St., MS-422,     Tel (781) 937-1924
Wilmington, MA 01887        Fax (781) 937-1014