RE: When does w change?

I agree without the cross there will be a delay between the zero crossing and the assign being performed but this delay depends on the analog timestepping mechanism. So the assign may not be evaluated on some of the digital timeticks, since the analog is not forced to evaluate every timetick.

Also, on the other side, if analog timesteps are much smaller than a digital timetick, the 'assign' will be evaluated at the timetick and will get the latest value of the analog variable 'e' (and not any of the intermediate changes to 'e').

Cheers,
Sri

-----Original Message-----
From: owner-verilog-ams@eda.org [mailto:owner-verilog-ams@eda.org] On Behalf Of Kevin Cameron
Sent: Saturday, 12 February 2005 12:21 PM
To: Jonathan David; verilog-ams@eda.org
Subject: RE: When does w change?

I would have thought there would be an event on e at every timestep. All the @cross does is make sure you get one at the moment the crossing occurs - i.e. without the @cross there will be some delay between the time sin($abstime) crosses 0 and the assign is performed.

Kev.

-----Original Message-----
From: owner-verilog-ams@eda.org [mailto:owner-verilog-ams@eda.org] On Behalf Of Jonathan David
Sent: Friday, February 11, 2005 4:12 PM
To: verilog-ams@eda.org
Subject: RE: When does w change?

 It would never have occurred to me to TRY that syntax.
What I would have used would be..
module x;
  real e;
  reg d = 0;
  wire w;
  analog e = sin($abstime);
  always @(cross(e)) d = (e > 0.0);
  assign w = d;
endmodule

Which I think is your intent..
and should enable you to answer the question.
Without the @cross, there is never an EVENT to drive the update in the digital side.

Jonathan David Mixed-Signal IC
jbdavid@cadence.com Ph (408)894-2646

-----Original Message-----
From: owner-verilog-ams@eda.org [mailto:owner-verilog-ams@eda.org] On Behalf Of Kevin Cameron
Sent: Friday, February 11, 2005 3:58 PM
To: Bakalar, Kenneth; verilog-ams@eda.org
Subject: RE: When does w change?

I would have thought the assign would be evaluated anytime e changes, which begs the question when does the analog statement get evaluated? - Is there a maximum/minimum timestep that applies here?

Kev.

-----Original Message-----
From: owner-verilog-ams@eda.org [mailto:owner-verilog-ams@eda.org] On Behalf Of Bakalar, Kenneth
Sent: Friday, February 11, 2005 3:00 PM
To: verilog-ams@eda.org
Subject: When does w change?

All,

Here is a puzzle. At what series of simulation times is the process associated with the "assign" executed?

module x;
  real e;
  wire w;
  analog e = sin($abstime);
  assign w = (e > 0.0);
endmodule

"6.1.2 The continuous assignment statement [Verilog 2001]

...Assignments on nets shall be continuous and automatic. This means that whenever an operand in the righthand side expression changes value, the whole right-hand side shall be evaluated and if the new value is different from the previous value, then the new value shall be assigned to the left-hand side..."

Regards,
Ken
Received on Sun Feb 13 23:07:41 2005