RE: Validation suite for Verilog-AMS

Oskar,

Simulator -specific testbenches are indeed needed, but they can be very 
minimal. As soon as it is verified that $display() works, most (if not 
all) of the tests can be done from Verilog-A itself. Using $fopen() and 
$fstrobe() the output files are actually completely simulator-independent.

The test suite should not test the embedding of Verilog-A in a SPICE-like 
simulator - it should test the Verilog-A language implementation.

Regards,
Marq


Marq Kole
Competence Leader Analog Simulation, Philips ED&T

owner-verilog-ams@eda.org wrote on 21-07-2005 17:01:33:

> Hello,
>      I have looked into this issue recently and found that simulator
> specific testbenches are required. 
> I am particularly interested in modules which can be used for 
> demonstrating the capability of the
> language, for training and regression testing. What would be 
> required is a set of validated and relevant modules,
> which are free of any copyright restrictions, thus users would be 
> free to adapt them to their specific needs.
> I am thinking of relatively simple modules, without second order 
> effects, such that direct commercial exploitation
> does not make much sense.
> I have looked at the modules provided on the EDA.org website, and 
> was rather disappointed regarding the
> quality, syntax and relevance. Currently I think the best source is 
> the LRM itself. However these examples
> also have issues, thus work would be required. A liberal copyright 
> policy from Accellera could help speed up
> getting these modules out into the public.
> Regards
>     Oskar
> 
> 
> From: owner-verilog-ams@eda.org [mailto:owner-verilog-ams@eda.org] 
> On Behalf Of Marq Kole
> Sent: Thursday, July 21, 2005 6:55 AM
> To: verilog-ams@eda.org
> Subject: Validation suite for Verilog-AMS

> 
> Hi, 
> 
> Would there by interest in setting up a validation-suite for 
Verilog-AMS? 
> 
> The idea is that a suite of tests for every Verilog-AMS language 
> construct is made that should result in output that is verifyable 
> against a benchmark. A specific subset of this suite should be 
> applicable to the Verilog-A analog language subset. With a simple driver 
for 
> 
> The driver for this idea is any Verilog-A or Verilog-AMS model that 
> is developed on a validated simulator has identical behaviour on any
> other validated simulator. A reason for Accellera in supporting and 
> driving this would be in increasing the proliferation of Verilog-AMS
> in as many simulators as possible thereby ensuring this standard 
> language indeed becoming a standard. 
> 
> The whole subset can be made largely simulator independent by 
> building up the test suite also from Verilog-A tests, making the 
> suite self-contained and less dependent on the actual ways of 
> integrating Verilog-A in each of the simulators. 
> 
> Maybe we can discuss this in one of the upcoming teleconferences - 
> although I've completely lost track of the dates, and I won't be 
> available for the coming three weeks. 
> 
> Regards, 
> Marq 
> 
> 
> Marq Kole
> Competence Leader Analog Simulation, Philips ED&T