Re: Validation suite for Verilog-AMS

Kevin,

I hadn't given much thought on the organization itself, I first wanted to 
see whether there was sufficient support in the Verilog-AMS committee to 
even start such an effort. I was thinking more along the lines of using 
the LRM structure as a basis for such a Validation Suite. I have 
constructed a few examples myself - for instance on the compiler 
directives and certain system tasks like idt(). That's no problem donating 
these, or donating others as we go along.

With such a Validation Suite in place any new proposals for language 
extensions could then come also with validation proposals that can be 
readily added to the validation suite. Even if there is no simulator yet 
implementing such a proposal, a test can be written that
exhibits its functionality, so that as soon as it is implemented (after 
approval) it can be verified against an accepted benchmark.

Regards,
Marq


Marq Kole
Competence Leader Analog Simulation, Philips ED&T


Kevin Cameron <kevin@sonicsinc.com> wrote on 21-07-2005 19:10:29:

> 
> Maybe we could break down the testsuite into more manageable chunks and 
> look for volunteers to do each chunk. If someone wants to propose a 
> directory hierarchy I can add it to the CVS repository at eda.org. Top 
> level areas (off the top of my head) might be Spice-compatibility and 
> Analog/Digital plug & play (the latter isn't too hard since you can use 
> the same digital testbench for multiple configurations). I see no 
> problem with Accellera sub-contracting some of the test generation, but 
> I think a lot of the tests would/should probably come from user 
> contribution if the intention is that the validation suite is to be 
> public-domain.
> 
> Given the nature of analog solvers, simulators are not going to behave 
> identically, so evaluating the results of tests may require more effort 
> than creating the tests, maybe Accellera needs to fund that part.
> 
> Maybe Marq could head a sub-committee to look after the effort?
> 
> Kev.
> 
> PS: There are a bunch of tests used to validate Icarus Verilog in the 
> gEDA distribution - http://www.geda.seul.org
> 
> David Smith wrote:
> 
> >I think this is a great goal. It has been discussed in many 
> different language efforts. The challenge has always been to get 
> either enough volunteer time or sufficient funding to make it work. 
> The latter is more successful.
> >
> >Are you thinking of having Accellera fund one or two people to 
> actually do the work?
> >
> >An important distinction you can make is feature tests (a different
> test for each language feature organized along the lines of the LRM)
> versus functional tests.
> >
> >Does anyone know of a public Verilog test suite that could be used 
> as a starting point? I am only aware of the VI test suite for VHDL.
> >
> >Regards
> >David
> >--------------------------
> >David W. Smith
> >Synopsys Scientist
> >W: 503.547.6467
> >M: 650.861.9814
> >
> >-----Original Message-----
> >From: owner-verilog-ams@eda.org <owner-verilog-ams@eda.org>
> >To: verilog-ams@eda.org <verilog-ams@eda.org>
> >Sent: Thu Jul 21 06:55:22 2005
> >Subject: Validation suite for Verilog-AMS
> >
> >
> >Hi, 
> >
> >Would there by interest in setting up a validation-suite for 
Verilog-AMS? 
> >
> >The idea is that a suite of tests for every Verilog-AMS language 
> construct is made that should result in output that is verifyable 
> against a benchmark. A specific subset of this suite should be 
> applicable to the Verilog-A analog language subset. With a simple driver 
for 
> >
> >The driver for this idea is any Verilog-A or Verilog-AMS model that
> is developed on a validated simulator has identical behaviour on any
> other validated simulator. A reason for Accellera in supporting and 
> driving this would be in increasing the proliferation of Verilog-AMS
> in as many simulators as possible thereby ensuring this standard 
> language indeed becoming a standard. 
> >
> >The whole subset can be made largely simulator independent by 
> building up the test suite also from Verilog-A tests, making the 
> suite self-contained and less dependent on the actual ways of 
> integrating Verilog-A in each of the simulators. 
> >
> >Maybe we can discuss this in one of the upcoming teleconferences - 
> although I've completely lost track of the dates, and I won't be 
> available for the coming three weeks. 
> >
> >Regards, 
> >Marq 
> >
> >
> >Marq Kole
> >Competence Leader Analog Simulation, Philips ED&T
> >
> >
> >
> > 
> >
>