SPICE compatibility issues

All,

With respect to the Verilog-AMS LRM Annex E on SPICE compatibility I would 
like to make a few comments - and a donation.

In table E.1 the names diode, bjt, mosfet, jfet and mesfet are essentially 
marked as specific use only, but at the same time their use in this 
particular form is prevented from occuring due to the limitations of 
SPICE-descendent circuit simulators - limitations, by the way, that do not 
apply to all analog circuit simulators . I think these names should be 
removed from the table E.1.

If a certain primitive is not available in a circuit simulator that 
supports Verilog-A(MS), it should be possible to create a module in 
Verilog-A that operates exactly like that particular primitive. In that 
way these primitives can be used in all Verilog-A(MS) and they really can 
be depended on to be available in an implementation.
This is possible for all primitives in the table E.1 except vpwl and ipwl. 
These two sources use a "wave" which is an arbitrary length array of 
time/value pairs. To make an Verilog-A implementation of such a source the 
arbitrary length array should be replaced with a parameter-length array, 
with the length parameter given before the array.

Now the donation: I have created Verilog-A versions of all primitives in 
table E.1 and I am willing to donate these to Accellera as a set of basic 
primitives that can be used in all simulators that support Verilog-A(MS). 
This also includes vpwl and ipwl, only with the modified interface that 
includes a length parameter. Would this be an acceptable addition to the 
standard or would it have to have another status?

Regards,
Marq


Marq Kole
Competence Leader Analog Simulation, Philips ED&T