Re: define and strings

Arpad -
In the Spice tradition, parameters can be varied -- eg,
you can sweep beta for a BJT and see how this affects
your circuit.  This doesn't quite fit the Verilog-AMS
paradigm, but nevertheless, you could have

prtest X1 #(.strParName("different string")) (.port1(a), .port2(b))
prtest X2 #(.strParName("yet another string")) (.port1(b), .port2(c))

where prtest is the name of the module that has the `PRT macro.

I would expect that the simulator would compile the module
and get $strobe(strParName), which would then get filled in
at elaboration time by the parameter overrides.

-Geoffrey



"Muranyi, Arpad" wrote:
> 
> Geoffrey,
> 
> Thanks for your explanation, it does start making
> sense.  But I sill have a question.  What if I modify
> your example this way:
> 
> parameter string strParName = "print a string";
> `define PRT(x) $strobe(x);
> `PRT(strParName)
> 
> What is $strobe(x) going to get from x?
> 
> $strobe("print a string") or
> $strobe(print a string)   or
> $strobe(strParName)       ?
> 
> Now I am getting the impression that it would be the
> last one, but before I though it should be the second.
> It all boils down to when strParName is evaluated, and
> I thought that would happen at compile time while the
> macro is expanded.
> 
> Thanks,
> 
> Arpad