Arpad - The R='any_valid_HSPICE_syntax_expression' doesn't really describe a resistor, I would argue. Also, the controlled sources in HSpice give you lots of rope to hang yourself, if you don't think about what you're doing. So, perhaps the problem isn't as intractable as you think. On the other hand, Sri was a little too optimistic, I think; if you try to go beyond {r, tc1, tc2} as parameters for the resistor, I've heard that some simulators compute leff as length + delta_l (delta_l is the change in length) and others as length -2 delta_l (delta_l is the extra amount etched off each end). The components with models (eg mosfet) are too much trouble. But I could well imagine someone writing a Verilog-A description of a mosfet model, and then wanting to add some parasitic elements using elements from Table E.1. -Geoffrey "Muranyi, Arpad" wrote: > > Sri, > > I think your assumption is wishful thinking, far from reality... > > The SPICE differences are not only syntactical, but also very > deeply technical. I mean the model equations may be completely > different. Even for a simple thing, such as a resistor, for > example, HSPICE has options for expressing it as a sheet > resistance, using geometric description, or the R=value, > or R='any_valid_HSPICE_syntax_expression' syntax. I am > not sure how many other SPICE flavors can do the sheet > resistance or free expression format. But when it comes > to the diode and transistor models, the picture gets even > worse. For one, HSPICE has a bunch of MOSFET levels > which may not be available in all other SPICE tools (or > vice versa), but add to that the proprietary company > SPICE flavors, such as Intel's or IBM's own home grown > SPICE tools and their own highly specialized and proprietary > equations.Received on Wed Jul 27 05:55:01 2005
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