Re: SPICE compatibility issues

On Tuesday 26 July 2005 07:27 pm, Muranyi, Arpad wrote:
> There is also a significant variation in the world of
> behavioral capabilities, the controlled sources.  Some can do
> derivatives and integrals, others can't.  Some have event
> triggered sources, others don't.  And guess what, my
> relentless questions on the `define and string parameters
> came from my desire to implement an HSPICE compatible syntax,
> in which a voltage or current source could be written this
> way:
>
>  E1  n1  n2  VOL='any_valid_HSPICE_syntax_expression'
>  I1  n1  n2  CUR='any_valid_HSPICE_syntax_expression'

I think I know enough about IBIS to understand some hidden 
meaning in Arpad's questions.

Verilog-AMS handles mixed language models in the way I was 
trying to promote for IBIS.  There are no language features for 
this explicit purpose.  Instead, an equivalence is documented.  
The requirement, which is met by the existing standard, is to 
be able to call a foreign model from Verilog, and a Verilog 
model from the foreign language.  That's all.  It isn't 
necessary to have a direct interface for everything.  You can 
make a wrapper.

IBIS uses a complex syntax for calling foreign language models.  
In addition to providing a call mechanism, the standard has 
restrictions on what primitives can be used in the called 
(foreign) model.  It is necessary to specify what foreign 
language is used, a choice of SPICE, Verilog-AMS, and VHDL_AMS.  
I think this was a mistake.  Just documenting an equivalence 
between the IBIS constructs and any one of the others would 
have been enough, and much easier, and better in the long run.  
Such an equivalence could also standardize how IBIS models are 
called from SPICE (and Verilog and VHDL).  My macro language 
proposal (for IBIS) would have done this, but it was rejected.

This example from HSPICE is an easy one.  Those components are 
not supported, but you can make a wrapper:

In HSPICE:

.subckt my_e1_wrapper n1 n2
E1  n1  n2  VOL='any_valid_HSPICE_syntax_expression'
.ends

Now from Verilog...

module my_module (n11 n22 n33);
	.....
	my_e1_wrapper  E1 (n1 n2);
	.....
endmodule