I don't think it's the Verilog-AMS committee's job to work out exactly how to migrate old simulator netlists into Verilog-AMS. The language itself should (as much as possible) support re-writing the primitive models of old simulators in portable Verilog-AMS - it's up to the vendors/users to do the translation. Going forward it would be good to have a standard library of models for use with Verilog-AMS that have well defined parameters and behavior that most vendors, users and foundaries agree on - I'm assuming these will look pretty much like the current popular device models used by the various Spice simulators, but are unlikely to match any specific Spice exactly. IMO the activity of defining and developing standard libraries should stay with Accellera, and the Verilog-AMS language development should move to an IEEE SystemVerilog subcommittee. Kev. > > >"Muranyi, Arpad" wrote: > > >>Sri, >> >>I think your assumption is wishful thinking, far from reality... >> >>The SPICE differences are not only syntactical, but also very >>deeply technical. I mean the model equations may be completely >>different. Even for a simple thing, such as a resistor, for >>example, HSPICE has options for expressing it as a sheet >>resistance, using geometric description, or the R=value, >>or R='any_valid_HSPICE_syntax_expression' syntax. I am >>not sure how many other SPICE flavors can do the sheet >>resistance or free expression format. But when it comes >>to the diode and transistor models, the picture gets even >>worse. For one, HSPICE has a bunch of MOSFET levels >>which may not be available in all other SPICE tools (or >>vice versa), but add to that the proprietary company >>SPICE flavors, such as Intel's or IBM's own home grown >>SPICE tools and their own highly specialized and proprietary >>equations. >> >> > > >Received on Wed Jul 27 10:01:46 2005
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