RE: SPICE compatibility issues

Geoffrey,

I agree, when you write something that can have any expression,
it is really not a resistor, capacitor, inductor, voltage or
current source any more.  So using a specific element type,
R, L, C, E, F, G, H doesn't make much sense, because you could
achieve the same results with practically any of these elements
if you write your equations accordingly.  But HSPICE has them,
and we were talking about compatibility, which means that we
need to address these features too if we want to be compatible.

Regarding your statement that "components with models (eg mosfet)
are too much trouble", the problem is that even the R, L, C
elements can have an associated .model in HSPICE.  If we leave 
these out too, we will end up supporting a very small subset
of the HSPICE capabilities.  This increases the probability for
incompatible, or non supported features, and this whole idea
of SPICE compatibility will go down the drain...  I had a lot
of experience with tools which claimed that they were HSPICE
compatible, and I could never get anything done with them,
because a SLIGHT LITTLE incompatibility always came in the way.

Arpad
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-----Original Message-----
From: geoffrey.coram@analog.com [mailto:geoffrey.coram@analog.com] 
Sent: Wednesday, July 27, 2005 5:55 AM
To: Muranyi, Arpad
Cc: verilog-ams@eda.org
Subject: Re: SPICE compatibility issues

Arpad -
The R='any_valid_HSPICE_syntax_expression' doesn't really
describe a resistor, I would argue.  Also, the controlled
sources in HSpice give you lots of rope to hang yourself,
if you don't think about what you're doing.  So, perhaps
the problem isn't as intractable as you think.

On the other hand, Sri was a little too optimistic, I think;
if you try to go beyond {r, tc1, tc2} as parameters for the
resistor, I've heard that some simulators compute leff as
length + delta_l (delta_l is the change in length) and others
as length -2 delta_l (delta_l is the extra amount etched off
each end).

The components with models (eg mosfet) are too much trouble.
But I could well imagine someone writing a Verilog-A 
description of a mosfet model, and then wanting to add some
parasitic elements using elements from Table E.1.

-Geoffrey