RE: bad syntax in example in section 6.6.2

Marq,
thanks for pointing this out - can you add this to the issues database;
 
http://www.eda.org/mantis/view_all_bug_page.php
 
--Martin


________________________________

	From: owner-verilog-ams@eda.org
[mailto:owner-verilog-ams@eda.org] On Behalf Of Marq Kole
	Sent: Monday, August 15, 2005 8:01 AM
	To: verilog-ams@eda.org
	Subject: bad syntax in example in section 6.6.2
	
	

	All, 
	
	I was just skimming through the open issues list Sri send around
on July 25 as an excel attachment. I have recently found about at least
one more (minor) issue that's not in this list. 
	
	In the example in section 6.6.2 on page 131 of the LRM
(genvarexp), the array terminal dt is defined with bad syntax. Instead
of: 
	
	  input dt[1:width]; 
	  electrical dt[1:width]; 
	
	it should be defined using: 
	
	  input[1:width] dt;
	 electrical[1:width] dt;
	
	I think this should be added to open issues list. 
	
	Marq Kole
	Competence Leader Analog Simulation, Philips ED&T