RE: proposal to resolve AMS - SystemVerilog logic conflict

Kevin,
I read over you proposal and it sounds like what you are proposing is
handled by the 'begin_keywords feature of SV.

(as FYI to others on the reflector) This macro directive allows users to
switch in and out different keyword sets and so enables users to avoid
keyword clashes in old legacy Verilog code.

e.g.;

`begin_keywords "1364-1995"

Changes the keyword set to be V1995.

Therefore users can do;

`begin_keywords "1364-1995"
`include "old.v"
`end_keywords

to import old verilog without the risk of keyword clashes;

Aside: I believe that AMS should leverage this functionality. I will
file an request in the database on this later.



However you say; "I don't like that much since it requires editing old
code to make it work with the new language."

This is not correct - with the proposal I made users can do this to get
old VAMS code to work;

`define VAMS_DISCRETE_DIS logic
`include "old.vams"

Concerns I have with the proposal you sent are

1. Also behind this proposal is that users will want to be able to
create modules with both AMS AND SV functionality.

Using typedefs to switch on and off the keyword logic is going to make
such modules pretty confusing and gross.

2. The SV committee have decided to make logic a keyword not a typedef
and they are in the process of balloting on this.

Thanks,
--Martin

-----Original Message-----
From: Kevin Cameron [mailto:kevin@sonicsinc.com] 
Sent: Friday, August 12, 2005 4:04 PM
To: Martin O'Leary
Cc: verilog-ams@eda.org
Subject: Re: proposal to resolve AMS - SystemVerilog logic conflict

Martin O'Leary wrote:

> 
>Here is my proposal to resolve AMS - SystemVerilog contradictory uses 
>of logic declarations Thanks, --Martin
>  
>
I don't like that much since it requires editing old code to make it
work with the new language.
Since the same problem applied to old digital Verilog I proposed a
different solution a long time ago
(http://www.eda.org/sv-ec/hm/1193.html). Basically all the standard
types are renamed to something unlikely to clash, and when the
compiler/parser starts it
(automatically) reads a header
file that typedefs the new types as the old e.g.:

    typedef  __sv_digital_logic logic;

Then if at a later time you want to read some old stuff you can do an
untypedef to forget that meaning of logic:

    untypedef logic;
     `include "old.v"
    typedef  __sv_digital_logic logic;

This shouldn't cause any problems for existing SV code, and doesn't
require old code to be changed (just wrapped by some untypedef/typedef
includes).

If you want to use the SV "logic" type with the current AMS logic type
you can use the built-in (__sv_digital_logic above) or typdef it to
something shorter.

It shouldn't take more than a few hours for someone with a SV parser to
try that out.

Kev.

>
>Problem: 
>AMS and SystemVerilog both use 'logic' in a contradictory way.
>
>This prevents people for mixed AMS and SystemVerilog in the same parse 
>stream.
>
>It also is going be a serious roadblock for creating SystemVerilog-AMS.
>
>In AMS, logic is discipline defined in the standard discipline header 
>file; disciplines.vams;
>
>	discipline logic
>	domain discrete;
>	enddiscipline
>
>To make declare a net called n as having logic discipline in AMS one 
>does;
>
>	logic n;
>
>SystemVerilog adds another 4-value data type, called logic (see 
>Sections
>3.3.2 and 5.6 of the SystemVerilog 3.1a LRM).
>
>To create a logic variable called n, one does;
>
>	logic n;
>
>Note logic is almost exactly identical to 'reg' except logic can be 
>declared inside other things (like a struct).
>
>
>Solution:
>
>We need to deprecate logic as a identified defined in disciplines.vams;
>
>In AMS, the definition of logic as a discrete discipline in 
>disciplines.vams should be removed.
>
>Also the following should be added the disciplines.vams to promote a 
>new standard discrete discipline called d_logic (short for discipline 
>logic) but allow users to switch back to using logic by putting 
>"'define VAMS_DISCRETE_DIS logic" before the include to 
>disciplines.vams in their sourcefiles.
>
>`ifdef VAMS_DISCRETE_DIS
>`else
>`define VAMS_DISCRETE_DIS d_logic
>`endif
>
>discipline `VAMS_DEFAULT_DISCRETE_DIS
>     domain discrete;
>enddiscipline
>
>All examples/text in the LRM that use logic should be changed to 
>d_logic.
>
>
>  
>