>From: Kevin Cameron <kevin@sonicsinc.com> >Very little progress seems to have been made on making [SystemVerilog] >compilation >modular like C/C++, so it is still the case that Verilog input in >multiple files is treated as >one single input stream, No, I don't believe this is still the case. I believe that the most recent P1800 draft standard requires implementations to support a mode where separately specified source files are treated as different compilation units. Since declarations outside of modules are in the scope of the compilation unit, this allows limiting the scope of definitions to source files. Steven Sharp sharp@cadence.comReceived on Tue Aug 16 11:43:02 2005
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