Steven Sharp wrote: >>From: Kevin Cameron <kevin@sonicsinc.com> >> >> >>Very little progress seems to have been made on making [SystemVerilog] >>compilation >>modular like C/C++, so it is still the case that Verilog input in >>multiple files is treated as >>one single input stream, >> >> > >No, I don't believe this is still the case. I believe that the most >recent P1800 draft standard requires implementations to support a mode >where separately specified source files are treated as different >compilation units. Since declarations outside of modules are in the >scope of the compilation unit, this allows limiting the scope of >definitions to source files. > >Steven Sharp >sharp@cadence.com > > > Maybe - but I'm sure a lot of stuff still depends on the old methodology too, and as you say that's only the latest draft, given practically nothing ever gets deprecated I'd assume that the old methodology will be supported for some years to come. Every cycle of AMS/SV upgrade adds new keywords, I feel we should make some attempt mitigate the name clash problem when we can, and I prefer to add generally useful mechanisms to the language rather than ad-hoc patches. Kev.Received on Tue Aug 16 13:06:44 2005
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