Re: proposal to resolve AMS - SystemVerilog logic conflict

As Martin has already noted, the built-in types in SV are keywords rather
than predefined typedefs.  This means that an "untypedef" would not help
in avoiding name conflicts with them.  There was resistance within the SV
committees to the suggestion of using a less common name for the built-in
types, with typedefs to get backward compatibility with code using the
older names.  So I wouldn't count on getting that changed.

However, there is an alternative way to work around this that gives a
similar effect.  You can use the `begin_keywords directive to turn off
the keywords for the built-in types, after using a typedef to create an
equivalent type.  For example:

typedef logic sv_logic;

`begin_keywords "1364-2005"

module top;
sv_logic [7:0] byte;
integer logic;
endmodule

`end_keywords

Steven Sharp
sharp@cadence.com