Re: proposal to resolve AMS - SystemVerilog logic conflict

Steven Sharp wrote:

>As Martin has already noted, the built-in types in SV are keywords rather
>than predefined typedefs.  This means that an "untypedef" would not help
>in avoiding name conflicts with them.  There was resistance within the SV
>committees to the suggestion of using a less common name for the built-in
>types, with typedefs to get backward compatibility with code using the
>older names.  So I wouldn't count on getting that changed.
>  
>
The proposal was to rename the built-in types to something wordy e.g. 
*__sv_logic*,
(which can be a keyword), and then have an initial typedef of that to 
*logic* (not a keyword)
which can be "forgotten" if necessary with an untypedef. As far as I can 
tell this should not
change the behavior of SV at all with respect to existing code.

>However, there is an alternative way to work around this that gives a
>similar effect.  You can use the `begin_keywords directive to turn off
>the keywords for the built-in types, after using a typedef to create an
>equivalent type.  For example:
>
>typedef logic sv_logic;
>
>`begin_keywords "1364-2005"
>
>module top;
>sv_logic [7:0] byte;
>integer logic;
>endmodule
>
>`end_keywords
>  
>
As I said before the mechanism I proposed is a general purpose way of 
limiting the
scope of various types. There is plenty of opportunity for users to 
create data-types that
will clash with other designers' types, disciplines or natures etc. 
which are likely to
make the source descriptions ambiguous (and unparsable).

*`begin_keywords* addresses the problem of keywords clashing for 
non-type constructs.

Kev.

>Steven Sharp
>sharp@cadence.com
>
>
>  
>