RE: hierarchical parameter passing in DC sweep

	Kevin,
	here are some additional comments prefixed by oleary2>
	thanks,
	--Martin 
	 
________________________________

	From: Kevin Cameron [mailto:kevin@sonicsinc.com] 
	Sent: Wednesday, August 24, 2005 4:44 PM
	To: Martin O'Leary
	Cc: Geoffrey.Coram; verilog-ams@eda.org
	Subject: Re: hierarchical parameter passing in DC sweep
	
	
	 .....  
	
	
	Not sure what you mean by a "global" parameter. 
	 
	oleary> This is a spice concept and is one of the two key issues
that the dynamic parameter seeks to address.
	I will explain it using the following pseudo-spice netlist;
	 
	* spice netlist
	 
	.parameter global1 = 5
	 
	X1 src 0 foo
	.....
	 
	.subckt foo a b
	parameter r = global1
	R 1 a b r=global1 
	.ends
	 
	A way to translate this to Verilog-AMS would be;
	 
	// verilog-ams netlist
	....
	 
	module top;
	parameter global1 = 5;
	 
	foo X1(gnd,src);
	....
	 
	endmodule
	 
	module foo (a,b);
	parameter r = top.global; // THIS IS A SYNTAX ERROR, you are not
allowed to use hierarchical references in parameter initializers. The
reason that this is difficult to change is that it makes the Verilog
parameter calculation algorithms even more complex than they already
are.
	 
	resistor #(.r(r)) R1(a,b);
	endmodule
	 
	 
	however this is a problem which is noted in the comment about
the syntax error above.
	 
	Thanks,
	--Martin