Verilog-AMS question regarding retention

Hello everyone,
 
It's been a while since I last wrote...
 
I found something in the LRM that seems to be a contradiction
to me.  Please help me to understand it, or if it is indeed
a problem in the LRM, I would like to request correction.
 
Section 5.3.1.3 of the LRM v2.2 says: 
 
"Contributing a flow to a branch which already has a value retained for the potential
results in the potential being discarded and the branch being converted to a flow source.
Conversely, contributing a potential to a branch which already has a value retained for
the flow results in the flow being discarded and the branch being converted into a
potential source. This is used to model switches. It is illegal to contribute to an external
switch branch from within an analog block."
 
However, the example in section 4.5.1 seems to contradict this:
 
"Examples:
 
To implement nodesets or initial conditions using the analysis function and switch
branches, use the following.
 
if (analysis("ic"))
  V(cap) <+ initial_value;
else
  I(cap) <+ ddt(C*V(cap));  "
 
 
This example gives me the impression that for some odd reason the
retention rule doesn't apply here, or has a different meaning, or
whatever...  Could someone please explain to me how to interpret
these sections in the LRM?
 
The reason I am hung up on this is because I have two simulators
which give me different results with a simple capacitor model I
wrote:
 
  analog begin
    if (analysis("static"))
      V(Out) <+ V0;
    else
      I(Out) <+ Scale * Cval * ddt(V(Out));
  end
 
One will retain the V0 value in the above code but the other
will not.  Which one is right?

Thanks,
 
Arpad
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