Re: Verilog-AMS question regarding retention

Arpad,

As geoffrey has pointed out the warning should come only if both flow 
and potential contribution are done to the same branch within the same 
iteration. You can either contribute to voltage (or) flow in a single 
iteration but not both - which is not the case when it comes to switch 
branches (as it happens in different iterations based on the value of 
the constant if-conditional expression).

Also, another point to note, the else condition on the switch branch is 
not strictly necessary. If you have the following piece code:

if (expr)
   V(out) <+ rhs_expr;

The above case also should be considered as a switch branch. The else 
condition is automatically assumed to be an open circuit ie. current 
contribution of zero (I(out) <+ 0;)

Ofcourse, this makes the code bit less clear and i would suggest to 
specify the else condition explicitly.

cheers,
Sri

Muranyi, Arpad wrote:
> Hello everyone,
>  
> It's been a while since I last wrote...
>  
> I found something in the LRM that seems to be a contradiction
> to me.  Please help me to understand it, or if it is indeed
> a problem in the LRM, I would like to request correction.
>  
> Section 5.3.1.3 of the LRM v2.2 says:
>  
> "Contributing a flow to a branch which already has a value retained for 
> the potential
> results in the potential being discarded and the branch being converted 
> to a flow source.
> Conversely, contributing a potential to a branch which already has a 
> value retained for
> the flow results in the flow being discarded and the branch being 
> converted into a
> potential source. This is used to model switches. It is illegal to 
> contribute to an external
> switch branch from within an analog block."
>  
> However, the example in section 4.5.1 seems to contradict this:
>  
> "Examples:
>  
> To implement nodesets or initial conditions using the analysis function 
> and switch
> branches, use the following.
>  
> if (analysis("ic"))
>   V(cap) <+ initial_value;
> else
>   I(cap) <+ ddt(C*V(cap));  "
>  
>  
> This example gives me the impression that for some odd reason the
> retention rule doesn't apply here, or has a different meaning, or
> whatever...  Could someone please explain to me how to interpret
> these sections in the LRM?
>  
> The reason I am hung up on this is because I have two simulators
> which give me different results with a simple capacitor model I
> wrote:
>  
>   analog begin
>     if (analysis("static"))
>       V(Out) <+ V0;
>     else
>       I(Out) <+ Scale * Cval * ddt(V(Out));
>   end
>  
> One will retain the V0 value in the above code but the other
> will not.  Which one is right?
> Thanks,
>  
> Arpad
> ====================================================================
>  

-- 
Srikanth Chandrasekaran
Design Technology (Adelaide)
Freescale Semiconductor
Ph: +61-(0)8-8168 3592 Fax: x3201