Re: Verilog-AMS question regarding retention

I know that the thread has become fairly long (and getting repetitive i 
guess), but from my understanding of the LRM on idt behavior:

1. The initial condition value (second arg of idt) is used only during 
DC step. So if the idt is not executed as part of the dc step/analysis 
("static"), then during transient we will never solve for the ic value 
(ofcourse unless the assert - 3rd argument, is true). I agree that the 
explanation in the table is little bit confusing as it doesnt explicitly 
state that "ic" will only be used in DC step.

2. People can use the assert flag to always set the ic condition for the 
idt the first time it is executed. I thought this should get around 
Marq's problem starting the idt from t0 with ic being calculated.

3. The example given below should give same results because Q0 (the 
initial conditial condition of idt) is specified in the else block of 
the analysis("static") which means idt doesnt get evaluated in DC and 
hence we never need the value of Q0. In this case, the initial condition 
is expected to be set by DC analysis and not required as part of the idt 
argument. I am assuming below the initial condition for that branch is 
just an open circuit (I(cap) <+ 0) (unless there are other nodesets on 
that branch), since it will be treated as an implicit switch branch.

cheers,
Sri





Muranyi, Arpad wrote:
> Now wait a minute...
> 
> I went back to the LRM and re-read the description in Section 4.4.5
> on the idt operator a few times.  This is what I "discovered".
> 
> Table 4-21 says:
> 
> ole0.bmp
> 
> In this row there is no IC in the "idt(expr)", so the "initial
> condition being computed in the DC analysis" in the comment refers
> to initial voltages and/or currents which will establish themselves
> in the simulation across the integral due to the rest of the circuit.
> This has nothing to do with IC in the idt() code.
> 
> ole1.bmp
> 
> In this row, the comments say "with the initial condition in/ ic/".
> This does not tell me that IC is only calculated during DC analysis.
> This to me means that IC should be part of the results no matter what.
> It is a different story that "In DC analysis,/ ic/ is returned".
> 
> So based on this, the two versions of my example should return
> different results!
> 
>   if (analysis("static"))
>     some stuff here;
>   else
>     V(cap) <+ idt(I(cap), Q0) / Cap_value;  // (this time I used Q0 to 
> be correct)
>   -------------------------------------------
>   if (analysis("static"))
>     some stuff here;
>   else
>     V(cap) <+ idt(I(cap)) / Cap_value;
> 
> Any comments?
> 
> Arpad
> =================================================
> 
>  
> 
> -----Original Message-----
> From: Muranyi, Arpad
> Sent: Wednesday, October 12, 2005 9:26 AM
> To: verilog-ams
> Subject: RE: Verilog-AMS question regarding retention
> 
> Marq,
> 
> This is an interesting detail I missed.  According to this:
> "with the initial condition computed or assigned in DC analysis"
> if the idt statement is not part of the initial condition
> calculations, it should return results as if IC was omitted,
> i.e. IC=0?  So the two examples below are supposed to CORRECTLY
> return the same results?
> 
>   if (analysis("static"))
>     some stuff here;
>   else
>     V(cap) <+ idt(I(cap), V0) / Cap_value;
>   -------------------------------------------
>   if (analysis("static"))
>     some stuff here;
>   else
>     V(cap) <+ idt(I(cap)) / Cap_value;
> 
> Is this the intention of the LRM, and considered the correct
> behavior?
> 
> Arpad
> =================================================================
> 
> This is an excellent point: the LRM says that the idt() operator
> should run from 0 to t, with the initial condition computed or
> assigned in DC analysis. Now what happens if the simulation
> starts at some other time, for instance to have some control logic
> in a particular state? It should start from t0, where t0 is the
> time value of the (implicit) DC analysis
> 

-- 
Srikanth Chandrasekaran
Design Technology (Adelaide)
Freescale Semiconductor
Ph: +61-(0)8-8168 3592 Fax: x3201