RE: Verilog-AMS question regarding retention

Now wait a minute...

I went back to the LRM and re-read the description in Section 4.4.5
on the idt operator a few times.  This is what I "discovered".

Table 4-21 says:

 <<ole0.bmp>> 

In this row there is no IC in the "idt(expr)", so the "initial
condition being computed in the DC analysis" in the comment refers
to initial voltages and/or currents which will establish themselves
in the simulation across the integral due to the rest of the circuit.
This has nothing to do with IC in the idt() code.

 <<ole1.bmp>> 

In this row, the comments say "with the initial condition in ic".
This does not tell me that IC is only calculated during DC analysis.
This to me means that IC should be part of the results no matter what.
It is a different story that "In DC analysis, ic is returned".

So based on this, the two versions of my example should return
different results!

  if (analysis("static"))
    some stuff here;
  else
    V(cap) <+ idt(I(cap), Q0) / Cap_value;  // (this time I used Q0 to be correct)
  -------------------------------------------
  if (analysis("static"))
    some stuff here;
  else
    V(cap) <+ idt(I(cap)) / Cap_value;

Any comments?

Arpad
=================================================

 

-----Original Message-----
From: Muranyi, Arpad 
Sent: Wednesday, October 12, 2005 9:26 AM
To: verilog-ams
Subject: RE: Verilog-AMS question regarding retention

Marq,

This is an interesting detail I missed.  According to this:
"with the initial condition computed or assigned in DC analysis"
if the idt statement is not part of the initial condition
calculations, it should return results as if IC was omitted,
i.e. IC=0?  So the two examples below are supposed to CORRECTLY
return the same results?

  if (analysis("static"))
    some stuff here;
  else
    V(cap) <+ idt(I(cap), V0) / Cap_value;
  -------------------------------------------
  if (analysis("static"))
    some stuff here;
  else
    V(cap) <+ idt(I(cap)) / Cap_value;

Is this the intention of the LRM, and considered the correct
behavior?

Arpad
=================================================================

This is an excellent point: the LRM says that the idt() operator 
should run from 0 to t, with the initial condition computed or 
assigned in DC analysis. Now what happens if the simulation 
starts at some other time, for instance to have some control logic 
in a particular state? It should start from t0, where t0 is the 
time value of the (implicit) DC analysis