Initial condition of idt()

Sri,

Thanks for your response.  Could you please point
to a location in the LRM where this is explained?

Thanks,

Arpad
=================================================

-----Original Message-----
From: Sri Chandra [mailto:srikanth.chandrasekaran@freescale.com] 
Sent: Wednesday, October 12, 2005 4:48 PM
To: Muranyi, Arpad
Cc: verilog-ams
Subject: Re: Verilog-AMS question regarding retention

...

1. The initial condition value (second arg of idt) is used only during 
DC step. So if the idt is not executed as part of the dc step/analysis 
("static"), then during transient we will never solve for the ic value 
(ofcourse unless the assert - 3rd argument, is true). I agree that the 
explanation in the table is little bit confusing as it doesnt explicitly 
state that "ic" will only be used in DC step.