RE: Verilog-AMS question regarding retention

Arpad,

The reason for noting this is in correlation with switch branches. Your 
example is perferctly legal as it is a genvar expression, but where 
earlier we were discussing retention and switch branches, I wanted to 
stress that with ddt() and idt() operators retention is not an issue as 
you cannot have a switch branch with these analog operators.

owner-verilog-ams@eda.org wrote on 12-10-2005 17:30:51:
> Mark,
> 
> I am not sure why you wrote this message.  Do you imply
> that the example I wrote is illegal?
> 
>   if (analysis("static"))
>     some stuff here;
>   else
>     V(cap) <+ idt(I(cap), V0) / Cap_value;
> 
> I know that analog operators cannot appear in IF statements,
> loop statements, and events if the condition expression is
> not genvar, but the LRM itself has an example for using ddt
> in an IF statement that is controlled by the analysis statement.
> 
>   if (analysis("ic"))
>     V(cap) <+ initial_value;
>   else
>     I(cap) <+ ddt(C*V(cap));
> 
> So what were you trying to say with your message below?
> 
> Thanks,
> 
> Arpad
> ========================================================
> 
> ________________________________
> 
> From: owner-verilog-ams@eda.org [mailto:owner-verilog-ams@eda.org] 
> On Behalf Of Marq Kole
> Sent: Tuesday, October 11, 2005 11:42 PM
> To: verilog-ams
> Subject: RE: Verilog-AMS question regarding retention
> 
> 
> 
> Arpad, 
> 
> The ddt() and idt() analog operators are not allowed inside 
> conditional statements, unless the condition expression is a genvar 
> expression, that is: it can be completely determined at compile 
> time. That means for instance that it cannot depend on a parameter 
> value or any expression depending on variables. This is in section 
4.4.1.
> 
> Marq Kole
> Competence Leader Analog Simulation, Philips ED&T
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> "Muranyi, Arpad" <arpad.muranyi@intel.com> 
> 
> Sent by: 
> owner-verilog-ams@eda.org 
> 
> 11-10-2005 18:22 
> 
> 
> To
>    "verilog-ams" <verilog-ams@eda.org> 
> cc
> 
> Subject
>    RE: Verilog-AMS question regarding retention 
> Classification
> 
> 
> 
> 
> 
> Thank you all who replied to my question on retention
> both publicly and privately.
> 
> From these responses I gather that the capacitor example
> shown in LRM v2.2 at the end of Section 4.5.1 must be
> correct.
> 
> However, I think there is a direct contradiction between
> this example and the one used to illustrate the "value
> retention" discussion in Section 5.3.1.3.  The two examples
> look almost the same, yet one supposed to illustrate how
> the previous values are discarded, and the other supposed
> to show how the initial condition is retained.  This doesn't
> make sense, and resulted in at least one CAD tool's implementation
> to be incorrect.  In this tool the initial condition of
> the capacitor model gets discarded at the second time step
> based on the example under 5.3.1.3.  I would like to request
> a correction to the LRM to make this clear.
> 
> In addition, it would be useful to describe how the past
> values of analog operators, such as ddt and idt are supposed
> to be resolved when they appear in conditional statements
> controlled by the analysis function.  For example, if I
> wrote the capacitor model using the integral form together
> with an analysis conditional statement:
> 
>   if (analysis("static"))
>     some stuff here;
>   else
>     V(cap) <+ idt(I(cap), V0) / Cap_value;
> 
> "my favorite simulator" ignores the V0 initial condition in
> the integral, because they only take it into consideration
> if the expression has been evaluated at t=0.  Since this
> code does not evaluate the integral at t=0, V0 gets ignored,
> which is clearly wrong from an electrical or mathematical
> point of view.  The LRM should give guidance on how to deal
> with these situations.
> 
> Thanks,
> 
> Arpad
> ============================================================
>