RE: Verilog-AMS question regarding retention

owner-verilog-ams@eda.org wrote on 12-10-2005 18:17:39:
> Jonathan and Marq,
> 
> This discussion is getting interesting.
> 
> 1)  I know the equation I wrote was incorrect from
> the electronics point of view, I should have used
> 
>     if (analysis("static"))
>       some stuff here;
>     else
>       V(cap) <+ idt(I(cap), Ccap*V0) / Cap_value;
>                             ^^^^^^^
> since Q=C*V.  I was just being sloppy, partially to
> make the code shorter.  The point was really not the
> electronics part, but the question about how to deal
> with the IC part of the integral in the context of
> the IF statement.  Sorry for the confusion it may
> have caused.
> 
> 2)  Thanks for the hints for how else this could
> have been written.  They may come handy in my work.
> However, the main point of this example was that
> Section 4.5.1 in the LRM doesn't spell out how to
> resolve the values retained in the "history" of the
> analog operators when the IF statement changes states.
> I think something should be added to that section to
> clarify this.
> 
> 3)  Also, aside from the subject of electronics and
> the retention across IF statement braches, what is
> the IC part of the integral supposed to do?  Should
> it be included EVEN if the idt statement was never
> evaluated during the operating point calculations
> (or at t=0 if it is possible to write such code),
> or not?  From an engineering point of view to me
> it seems that it should be included all the time,
> but my favorite simulator doesn't do it.  Who is
> correct?

A solution to a first-order integral requires one boundary condition to be 
completely specified, so that is what the ic is for -- it is always 
present, but unspecified it defaults to the DC solution. My interpretation 
is therefore that after the implicit DC the ic is not taken into account 
anymore.
 
> 4)  One sentence in explanation below raised my eye
> brows:  "Because the branch does not switch between
> flow and potential, the DC value should be retained."
> 
> This whole thread was started by an issue I ran across
> with the subject of retention.  My in-house tool developer's
> interpretation was that the V0 assignment had to be discarded
> because the other branch of the IF statement was a flow
> assignment in my capacitor model:
> 
> if (analysis("static") begin
>    V(cap) <+ V0;
> end else begin
>    I(cap) <+ ddt(V(cap)) * Ccap;
> end
> 
> According to the responses I received to my first message,
> V0 should carry over (retained) BECAUSE the two assignments
> are never evaluated within the same time step.  The sentence
> that raised my eye brow seems to imply something else.
> I feel I am back to square one with my original question.
> 
> When does the simulator supposed to retain or discard?

It is not possible to provide contributions to both flow and potential of 
the same branch. Rentention in my view seems to be about whether the 
previous values - used in the analog solver for Verilog-A - are kept in 
subsequent time steps. If a switch branch occurs, there is no retention; 
as far as I can tell, for analog operators retention is a requirement for 
their correct operation.

> Does the sentence in Section 5.3.1.3 "Contributing a flow
> to a branch which already has a value retained for the
> potential results in the potential being discarded and
> the branch being converted to a flow source." apply to
> anywhere, any time in the entire simulation, or just
> within one time step?

I think I start to understand your question. Could I rephrase your 
question as to what retention means?

Is it that:

a. If you provide contribution statements to both flow and potential 
branches, only the last one will be used in the solution. So:

  branch b_in(plus, minus);
  branch b_out(plus, minus);

  analog begin
    V(b_out) <+ I(b_in) * R;
    I(b_out) <+ V(b_in) / R;
  end

would result in just one resistance, not two.

b. If you provide a contribution statement in one time-step to the flow of 
a branch and in the next to the potential of the same branch, the previous 
values (and derivatives) of the flow will be discarded, as these 
should/can not influence the solution of the potential.

  branch b_sw(ctrl, gnd);
  branch b_out(plus, minus);

  integer closed;

  analog begin
    closed = (V(b_sw) > vth ? 1 : 0);

    if (closed)
      V(b_out) <+ 0;
    else
      I(b_out) <+ 0;
    end

Like shown in the example in 5.1.5.

c. Is the switch from implicit DC to regular transient (detected through 
the analysis() task) similar to an ordinary time-step, or is it a special 
situation?

  branch b_cap(plus, minus);

  analog 
    if (analysis("ic"))
      V(b_cap) <+ initial_value;
    else
      I(b_cap) <+ ddt(C * V(b_cap));
  end

By the way, analog operators are not allowed in conditional or case 
statements, but the LRM says nothing about the use of relational or 
equality operators, like in:

  branch b_sw(ctrl, gnd);
  branch b_1(plus, minus);
  branch b_2(plus, minus);

  analog
    V(b_1) <+ (V(b_sw) == 1) * I(b_1) * Rmin;
    I(b_2) <+ (V(b_sw) == 0) * parasitic_cap * ddt(V(b_2));
  end

This would be a switch with resistance in the on-state and parasitic 
capacitance in the off-state.

> 
> Thanks
> 
> Arpad
> ========================================================
> 
> 
> ________________________________
> 
> From: owner-verilog-ams@eda.org [mailto:owner-verilog-ams@eda.org] 
> On Behalf Of Marq Kole
> Sent: Wednesday, October 12, 2005 1:12 AM
> To: verilog-ams
> Subject: RE: Verilog-AMS question regarding retention
> 
> 
> 
> Jonathan David <j.david@ieee.org> wrote on 12-10-2005 09:32:59:
> > the other exception (at least in my recollection of
> > the earlier Verilog-A spec) was that they ARE also
> > allowed inside "analysis" conditionals, like the one
> > Arpad was talking about. 
> > 
> > But the extreme case Arpad was talking about - 
> > NOW I know was was really strange.. 
> > V(cap) <+ idt(I(cap),V0) / Ccap;
> > the initial value of the IDT should be a CHARGE..
> > Not a voltage.. 
> 
> The initial condition is not an initial value of the idt() operator 
> but a boundary condition of the integral: as such it truly is a voltage 
> as it is the very first value out of the idt() operator that is 
> contributed to a voltage branch. 
> 
> > but even if you have 
> > ----
> > if (analysis("static"))
> >    Qc0 = V0*Ccap;
> > else begin
> >    V(cap) <+ idt(I(cap),Qc0)/Ccap;
> > end
> > ---
> > the integral should be evaluated at time 0 of the
> > transient, even if not during the DC .. 
> > 
> > But there is no real reason for this to be in the Else
> > clause.. 
> > if (analysis("static"))   Qc0 = V0*Ccap;
> >    V(cap) <+ idt(I(cap),Qc0)/Ccap;
> > 
> > or even 
> > real Qc0 = V0*Ccap;// this sets the initial value
> > analog begin
> >      V(cap) = idt(I(cap),Qc0)/Ccap; 
> > // initial value of idt used in static 
> > // so V(cap) = Qc0/Ccap = V0*Ccap/Ccap = V0;
> > //
> > should 
> > if (analysis("static") begin
> >    V(cap) <+ V0;
> > end else begin
> >    V(cap) <+ idt(I(cap))/Ccap;
> > end
> > have the exact same effect ? 
> 
> Now this is an interesting construction: the DC solution should act as 
> the initial condition of the transient -- that's what we do an implicit 
DC 
> for. Because the branch does not switch between flow and potential, the 
> DC value should be retained. In my interpretation of the standard, I 
would 
> say that the above two are equivalent. 
> 
> My favorite simulator says something else, but then I think my favorite 
> simulator is in error... 
> 
>