Re: Static connections to input ports

Bresticker, Shalom wrote:

>In Verilog, by default, the connection strength is 'strong'.
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>Shalom
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I'll take your word for it, but I would have assumed that since the 
obvious physical
implementation of a constant value is connecting the wire(s) to power or 
ground the
default strength would be 'supply'. Might be worth adding strength to 
the constant
definition if that's not already possible - D2A conversion of a strong-1 
and a supply-1
can be significantly different.

Kev.

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>>BTW, all connections are static (there are no dynamic
>>connections). What you probably need in the text is that a
>>constant value connected as above is equivalent to a driver of
>>the equivalent type in the module where it is used (testbench),
>>with a strength of "supply".
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