Re: Static connections to input ports

but this isn't initialization.. its creating a DC
source.. and I should be free to choose a voltage or
current or other nature source.. 
as often as I would use a voltage for a supply bias, I
would use a current for bias testing.. 
I wouldn't want an assumption made as to the nature 
or even discipline being used. 

If the discipline and nature declared are different
than that used below, do we assume that a
connect_module can be inserted? if so and you have
wreal2electrical cm's you can declare it as wreal
(with a simple real value) and let everything else be
handled by your cm's which can assume that wreal value
maps to the voltage.. 

If you explicitly define a static electrical (or other
two nature discipline) then you need to be clear (and
explicit) which access function is being used. 
thats my opinion.
jbdavid



Jonathan
--- Sri Chandra
<srikanth.chandrasekaran@freescale.com> wrote:

> 
> The constant number i think should reflect the
> voltage, similar to 
> initialization of the net.
> 
> electrical inout netA = 1.2;
> 
> I am thinking the above would reflect the voltage
> value rather than 
> current, treating it like a nodeset value.
> 
> cheers,
> Sri
> 
> Jonathan David wrote:
> > Helwig,
> > 
> > Other than the confusion on p2 (Logic or wreal?)
> > I don't know if "3.1" is the voltage or the
> current on
> > the electrical port.. 
> > Assuming this would be a shortcut for
> > electrical net01
> > V(net01) <+ 3.1;
> > example I2 (`1b1, 0.1, net01);
> > so you would need to provide something like.. 
> > example I2 (`1b1, 0.1, electrical(V(3.1)) );
> > 
> > ---
> > In general this could be setup.. but I think
> > you would need to provide more than the value.. 
> > you need the discipline, and the nature you are
> > setting. It could be more valuable for the 
> > wreal side, but I'm not sure if its that big a
> help
> > to testbench developers.. but I guess if it were 
> > in the language, I'd use it occasionally.
> > Jonathan
> > 
> > --- Helwig Graham-A11558
> <Graham.Helwig@freescale.com>
> > wrote:
> > 
> > 
> >>Hello,
> >>
> >>The Verilog language seems to allow the connection
> >>of a 4-state value to discrete input port within a
> >>module instantiation. See the first port
> connection
> >>in the example below. This type of port connection
> >>is very useful. The syntax of port connections in
> >>  
> >>  
> >>     module example(p1, p2, p3);
> >>         input p1; logic p1; wire p1;
> >>         input p2; wreal p2;
> >>         input p3; electrical p3;
> >>     endmodule
> >>  
> >>NOTE: The static values in these wreal and
> >>continuous input port connections are handled in
> the
> >>same way as initialization values in explicit
> wreal
> >>and continuous net declarations.
> >>  
> >>Should the merged Verilog-AMS/2005 LRM support the
> >>static connections to all types of input ports?
> >>  
> >>Regards 
> >>Graham Helwig
> >>AMS Verification Engineer
> >>Australia SoC Technology Centre
> >>Freescale Semiconductor
> >> 
> >>Phone: +61-8-81683532
> >>Fax: +61-8-81683201
> >>Email: graham.helwig@freescale.com
> >>
> > 
> > 
> 
> -- 
> Srikanth Chandrasekaran
> Design Technology (Adelaide)
> Freescale Semiconductor
> Ph: +61-(0)8-8168 3592 Fax: x3201
>