RE: Static connections to input ports

The mechanism in Verilog is that a port connection implicitly describes
a continuous assignment. In a real continuous assignment, you can
specify strength. In a port connection, you cannot.

The exception is when port collapsing occurs. If instead of connecting
the input port to a constant, you connect it to a wire of strength
supply, and if port collapsing occurs, then the supply strength will
propagate. In principle, port collapsing is optional. In practice, it
usually occurs, but there are exceptions.

Shalom


>-----Original Message-----
>From: owner-verilog-ams@eda.org [mailto:owner-verilog-
>ams@eda.org] On Behalf Of Kevin Cameron
>Sent: Monday, November 28, 2005 11:53 PM
>To: Bresticker, Shalom
>Cc: edaorg@v-ms.com; verilog-ams@eda.org;
>Graham.Helwig@freescale.com
>Subject: Re: Static connections to input ports
>
>Bresticker, Shalom wrote:
>
>>In Verilog, by default, the connection strength is 'strong'.
>>
>>Shalom
>>
>>
>I'll take your word for it, but I would have assumed that since
>the
>obvious physical
>implementation of a constant value is connecting the wire(s) to
>power or
>ground the
>default strength would be 'supply'. Might be worth adding
>strength to
>the constant
>definition if that's not already possible - D2A conversion of a
>strong-1
>and a supply-1
>can be significantly different.
>
>Kev.
>
>>
>>
>>
>>>BTW, all connections are static (there are no dynamic
>>>connections). What you probably need in the text is that a
>>>constant value connected as above is equivalent to a driver
>of
>>>the equivalent type in the module where it is used
>(testbench),
>>>with a strength of "supply".