RE: Static connections to input ports

Hello David,

> Other than the confusion on p2 (Logic or wreal?) I don't know 
> if "3.1" is the voltage or the current on the electrical port.. 
> Assuming this would be a shortcut for
> electrical net01
> V(net01) <+ 3.1;
> example I2 (`1b1, 0.1, net01);
> so you would need to provide something like.. 
> example I2 (`1b1, 0.1, electrical(V(3.1)) );

I think it is unnecessary to explicit define the discipline for any this type of port connection. The discipline can be obtained from the port it connects to using the existing discipline resolution methods in section 8 of the Verilog-AMS LRM. This will avoid the need for connectmodule insertion also.

I would consider the following modules to be equivalent: 

   module testbench();
          example i1(1'b1, 0.1, 3.1);
   endmodule

   module testbench();
 	    logic n1; reg n1;
	    initial n1 = 1'b1;
	    logic n2; wreal n2;
	    assign n2 = 0.1;
	    electrical n3;
	    analog V(n3) <+ 3.1;
          example i1(n1, n2, n3);
    endmodule
 
For this type of the continuous port connections, I would treat this value (3.1) as a potential contribution w.r.t. ground since every continuous discipline has a potential nature (conservative or signal-flow) and the flow nature is optional. 

Regards
Graham