RE: Static connections to input ports

Hm.. I disagree.. the lower level block may have
multiple representations with different definitions.. 
and I don't know which one of them is being used when
I look at (compile) this module.. 
I can't depend on the source for the DUT being
available at the time I first analyze the testbench.. 
and I want the behavior to remain the same no matter
which representation of the DUT I use.  
 (one may have wreal and another electrical.. 
I would want a way to distinguish the wreal static
value from the electrical one.. 

Since the implicit (pin order based) format is rarely
used, (at least by me!! why do you think I want to get
away from spice netlists !)

test #(.par1(1.0)) Inst3 (.a(1), .b(2.0),
.c.potential(3.0));

But I'd like the use of an access function better.. 
(it at least is associated with a specific nature..
then you can use any of the compatible disciplines at
elaboration... and its different than a wreal.. 

test #(.par1(1.0)) Inst3 (.a(1), .b(2.0), .c.V(3.0));

BTW I was unaware that a potential nature was
required. the 1.0 language spec I did much of my early
learning on just required at least 1 nature as far as
I recall.. 
 Jonathan

--- Helwig Graham-A11558 <Graham.Helwig@freescale.com>
wrote:

> Hello David,
> 
> > Other than the confusion on p2 (Logic or wreal?) I
> don't know 
> > if "3.1" is the voltage or the current on the
> electrical port.. 
> > Assuming this would be a shortcut for
> > electrical net01
> > V(net01) <+ 3.1;
> > example I2 (`1b1, 0.1, net01);
> > so you would need to provide something like.. 
> > example I2 (`1b1, 0.1, electrical(V(3.1)) );
> 
> I think it is unnecessary to explicit define the
> discipline for any this type of port connection. The
> discipline can be obtained from the port it connects
> to using the existing discipline resolution methods
> in section 8 of the Verilog-AMS LRM. This will avoid
> the need for connectmodule insertion also.
> 
> I would consider the following modules to be
> equivalent: 
> 
>    module testbench();
>           example i1(1'b1, 0.1, 3.1);
>    endmodule
> 
>    module testbench();
>  	    logic n1; reg n1;
> 	    initial n1 = 1'b1;
> 	    logic n2; wreal n2;
> 	    assign n2 = 0.1;
> 	    electrical n3;
> 	    analog V(n3) <+ 3.1;
>           example i1(n1, n2, n3);
>     endmodule
>  
> For this type of the continuous port connections, I
> would treat this value (3.1) as a potential
> contribution w.r.t. ground since every continuous
> discipline has a potential nature (conservative or
> signal-flow) and the flow nature is optional. 
> 
> Regards
> Graham
>