Re: Static connections to input ports

Helwig Graham-A11558 wrote:

>Hello Kev,
>
>  
>
>>I doubt "input p2; logic p2; wreal p2;" is allowed or 
>>feasible since it's hard to seperate the usage as real or 
>>logic syntactically, and there are no resolution rules for 
>>wreal and logic.
>>    
>>
>
>I treat wreal as just another discrete net type (i.e. wire). The only difference I see is that wreal nets have a few more restriction that the other net types. Declaring a discrete discipline with a wreal net type can be very useful in a design, particularly when 2 wreal nets need to be incompatible with each other.  
>  
>
IMO wreal was an unecessary hack introduced by Cadence to be compatible 
with stuff they had already implemented and shipped. You can achieve the 
same functionality with wires and signal-flow disciplines. If we ever 
get the SV syntax/semantics for binding an arbitrary (user defined) type 
to a wire sorted out I expect wreal to be deprecated.

>I think the discipline resolution and connect module should not be limited to discrete and continuous, instead it should expand to handled an 2 incompatible nets regardless of domain.
>  
>
Of course, it would be nice to be able to have (say) an 
electrical/optical connection have an opto-coupler module auto-inserted, 
but that kind of "connect module" is something that represents real 
hardware (a transducer) rather than a simulation artifact, so it would 
be a significant language extension. As yet no-one has proposed any 
schemes for providing resolution functions for user defined types in SV 
so I suspect it will be some time before we get as far as a general 
cross-domain/cross-type connection scheme.

BTW, the last presentation I saw on the future of SV indicated that 
there might not be a single (System)Verilog LRM, but rather the SV and 
Verilog LRMs would continue as seperate entities, so targeting Verilog 
200X for AMS might be problematic if your goal  is actually merging with SV.

Kev.

>Regards
>Graham
>