RE: Definition of integer division

In 4-state arithmetic, an integer is the same as "reg signed [31:0]".
One or all of the bits can indeed be x. In the case of division by 0,
all bits become x.

Shalom

> -----Original Message-----
> From: owner-verilog-ams@eda.org [mailto:owner-verilog-
> ams@eda.org] On Behalf Of Geoffrey.Coram
> Sent: Wednesday, December 14, 2005 11:42 PM
> To: Kevin Cameron; Verilog-A Reflector
> Subject: Re: Definition of integer division
> 
> Div by zero should be an error, whether integer or real.
> 
> What happens when I write this:
> 
> integer a, res;
> a = 0;
> res = 5 + (1/a);
> 
> 1/a is now "x" but then is converted/coerced to integer(?)
> for addition with 5.  What is the result of that "conversion"?
> How do you make "x" an integer?  Do you get an error because
> the simulator can't convert it to an integer?  That's sort of
> indirect.
> 
> -Geoffrey
> 
> 
> 
> Kevin Cameron wrote:
> >
> > Not much you can do about integer division by zero.
> Presumably this will
> > have to be addressed in SV which supports 2-state types
> (where x cannot
> > be the result) - I can't remember it coming up.
> >
> > Kev.