RE: Verilog-AMS Call Minutes - 18th April 2006

In IEEE Std 1800-2005:

"3.6 String literals

A string literal is enclosed in quotes and has its own data type.
Nonprinting and other special characters are preceded with a backslash.
SystemVerilog adds the following special string characters:

\v vertical tab
\f form feed
\a bell
\x02 hex number

A string literal must be contained in a single line unless the new line
is immediately preceded by a \ (backslash). In this case, the back slash
and the new line are ignored. There is no predefined limit to the length
of a string literal.

A string literal can be assigned to an integral type, as in Verilog. If
the size differs, it is right justified.

byte c1 = "A" ; bit [7:0] d = "\n" ;
bit [0:11] [7:0] c2 = "hello world\n" ;

...

SystemVerilog also includes a string data type to which a string literal
can be assigned. Variables of type string have arbitrary length; they
are dynamically resized to hold any string. String literals are packed
arrays (of a width that is a multiple of 8 bits), and they are
implicitly converted to the string type when assigned to a string type
or used in an expression involving string type operands (see 4.7)."

Shalom


> Section 2.6:
>    - (Action: Sri) check for Strings definition on SV (check SV