RE: Why is type for string parameters mandatory?

Geoffrey,

> In AMS LRM 2.2, Section 3.2.1 page 27, it says "it shall be an error
> to assign a numeric value to a parameter declared as string or to
> assign a string value to an integer or real parameter, whether that
> parameter was declared as integer or real or had its type derived
> from the type of the value of the constant expression."

[SB] However, in 1364/1800, it IS legal to assign a string LITERAL to an
integer.

> In 1800-2005, one has the statement (in 6.3.2):
>   In an assignment to, or override of, a parameter without
>   an explicit type declaration, the type of the right-hand
>   expression shall be real or integral.
> 
> I believe that "an explicit type declaration" is one like
>   parameter string mystr = "hi";
> and that, therefore, 1800 has the same requirement on
> string parameters as was added in AMS LRM 2.2.  (I believe
> that
>   parameter mystr = "hi";
> is an assignment as well as a declaration, and thus is
> illegal per the statement above.

[SB] However, 1800 4.7 says,
"Verilog supports string literals, but only at the lexical level. In
Verilog, string literals behave like packed arrays of a width that is a
multiple of 8 bits. A string literal assigned to a packed array of an
integral variable of a different size is either truncated to the size of
the variable or padded with zeroes to the left as necessary.
In SystemVerilog, string literals behave exactly the same as in
Verilog."

However, the clinching proof is that of back compatibility. That
statement in 6.3.2 was not meant to exclude string literals. String
literals are considered integral values in that context.

Shalom