Re: multiple analog blocks

edaorg@v-ms.com wrote:
> 
> I see you're still stuck with the idea that analog or digital owns
> something rather than it being shared.

Seeing as how this is stated in 8.2 Fundamentals (actually, 8.2.2)
in the mixed signal chapter of the LRM, I think you can't just
say it's a bad mental picture.


> I didn't think Verilog-A was a proper language now that Verilog-AMS is
> out, and any half decent simulator should be able to read a bunch of
> variable assignment statements in a simple  initial-begin-end block even
> if it can't do the rest of the digital stuff.

A major benefit of Verilog-A (over VHDL-AMS) is, in fact, that it *is*
a proper language, with a well-defined subset defined in the LRM.
There are a number of analog-only simulators, whether internal to
semiconductor companies or developed by smaller EDA companies that
don't want/need to spend the time implementing all the digital stuff --
particularly when this whole exercise would be a distraction from what
really needs to be done, in terms of generating a robust dependency tree.

-Geoffrey